arm-none-eabi-as --warn --fatal-warnings -g *.s -o s.o
arm-none-eabi-objdump --disassembler-options=force-thumb -Dxs s.o > s.list

arm-none-eabi-gcc -mcpu=cortex-m0plus -c -O3 *.c -o c.o
arm-none-eabi-objdump --disassembler-options=force-thumb -Dxs c.o > c.list

arm-none-eabi-ld -nostdlib -nostartfiles -T main.ld *.o -o main.elf
arm-none-eabi-objdump --disassembler-options=force-thumb -dxs main.elf > main.list
pico-elf2uf2 main.elf main.uf2
		

These commands will:

1. Assemble all assembly code files (.s) into object file s.o.
2. Compile (but do not link) all C language code files (.c) into object file c.o.
3. Link all object files into elf file main.elf according to linker script main.ld. This includes not only the two object file we just created from assembly and C language source code, but also pre-generated object files in the working directory, such as the SDK bootloader (boot2.o).
4. Generate the uf2 file main.uf2 from the elf file main.elf, that can be downloaded to RP2040 via USB.

MEMORY {
	FLASH(rwx) : ORIGIN = 0x10000000, LENGTH = 2048k
	SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 256k
	SRAM_4(rwx) : ORIGIN = 0x20040000, LENGTH = 4k
	SRAM_5(rwx) : ORIGIN = 0x20041000, LENGTH = 4k
	SRAM_0(rwx) : ORIGIN = 0x21000000, LENGTH = 64k
	SRAM_1(rwx) : ORIGIN = 0x21010000, LENGTH = 64k
	SRAM_2(rwx) : ORIGIN = 0x21020000, LENGTH = 64k
	SRAM_3(rwx) : ORIGIN = 0x21030000, LENGTH = 64k
}

ENTRY(_boot_start)

SECTIONS {
	.boot : {
		*(.boot2)
		*(.boot3)
	} > FLASH
	_boot_start = ORIGIN(FLASH);
	_boot_end = _boot_start + SIZEOF(.boot);

	.core0 : {
		. = ALIGN (256);
		*(.c0_vector)
		*(.c0_data)
		*(.c0_text)
	} > SRAM_4 AT > FLASH
	_core0_dest = ORIGIN(SRAM_4);
	_core0_start = _boot_end;
	_core0_end = _core0_start + SIZEOF(.core0);

	.core1 : {
		. = ALIGN (256);
		*(.c1_vector)
		*(.c1_data)
		*(.c1_text)
	} > SRAM_5 AT > FLASH
	_core1_dest = ORIGIN(SRAM_5);
	_core1_start = _core0_end;
	_core1_end = _core1_start + SIZEOF(.core1);

	.unspecified : {
		*(.text)
		*(.data)
		*(.bss)
	}
	ASSERT(!(SIZEOF(.unspecified)), "Unspecified text, data, and/or bss section")
}
		

We had discussed this linker script in my previous article: Compare RP2040 Executable Memory Regions and Load Program From Flash into SRAM. In conclusion:

• Place the SDK 2nd stage bootloader in the beginning of flash (address 0x10000000), followed by our 3rd stage bootloader.
• Then, place contents of core 0 in flash, vector table .c0_vector first (so it can be 256-byte aligned after loading into SRAM), followed by data .c0_data and program instruction .c0_text. Assign them the address of SRAM bank 4 (0x20040000).
• Next, place contents of core 1 in flash, vector table .c1_vector first, followed by data .c1_data and program instruction .c1_text. Assign them the address of SRAM bank 5 (0x20041000).

.cpu cortex-m0plus
.thumb
.align 2
.thumb_func
		

In this program, we will not use any assembly language code. However, we have to create an "empty" assembly code file just to satisfy the compile commands.

The first 16 vectors are required by ARM Cortex M0+ CPU.

Followed by a set of IRQ service routine addresses. This is implementation dependent because different implementations can have different peripherals. Details can be found in the RP2040 document.

We can create a header file vector.h to store the address of each vector:

#define vector_sp			0
#define vector_reset		1
#define vector_nmi		2
#define vector_hardfault	3
#define vector_svcall		11
#define vector_pendsv		14
#define vector_systick		15
#define vector_irq(n)		(16 + n)

#define irq_timer0		0
#define irq_timer1		1
#define irq_timer2		2
#define irq_timer3		3
#define irq_pwmwrap		4
#define irq_usbctrl		5
#define irq_xip			6
#define irq_pio00			7
#define irq_pio01			8
#define irq_pio10			9
#define irq_pio11			10
#define irq_dma0			11
#define irq_dma1			12
#define irq_io_bank0		13
#define irq_io_qspi		14
#define irq_sio_proc0		15
#define irq_sio_proc1		16
#define irq_clocks		17
#define irq_spi0			18
#define irq_spi1			19
#define irq_uart0			20
#define irq_uart1			21
#define irq_adc			22
#define irq_i2c0			23
#define irq_i2c1			24
#define irq_rtc			25
			

__attribute__((long_call)) extern void boot3_clearInterprocessorMailboxRx();

void c0_reset() __attribute__((section(".c0_text"))) __attribute__((naked));

void c0_reset() {
	(boot3_clearInterprocessorMailboxRx + 1)();
			

Define the entry point for core 0, function c0_reset.

This function will never return; therefore, it is not necessary to preserve the calling stack. We can make it naked, this tells the compiler to not generate code that preserves the calling stack.

Place this function in section .c0_text.

Before we perform any actual operations, we want to empty the inter-processor mailbox that may be contaminated during core 1 launch protocol. To do so, we will call the function boot3_clearInterprocessorMailboxRx, saved in boot3.o.

#define reg(reg_name)		(*(uint32_t volatile * const)(reg_name))
#define reg_xor(reg_name)	(*(uint32_t volatile * const)(reg_name + 0x1000))
#define reg_set(reg_name)	(*(uint32_t volatile * const)(reg_name + 0x2000))
#define reg_clr(reg_name)	(*(uint32_t volatile * const)(reg_name + 0x3000))
			

Recall that, the AHB-Lite Crossbar supports atomic register access. To do so, add an offset to the register address.

#define reg_resets_reset			0x4000c000
#define reg_resets_reset_usbctrl		24
#define reg_resets_reset_uart1		23
#define reg_resets_reset_uart0		22
#define reg_resets_reset_timer		21
#define reg_resets_reset_tbman		20
#define reg_resets_reset_sysinfo		19
#define reg_resets_reset_syscfg		18
#define reg_resets_reset_spi1			17
#define reg_resets_reset_spi0			16
#define reg_resets_reset_rtc			15
#define reg_resets_reset_pwm			14
#define reg_resets_reset_pll_usb		13
#define reg_resets_reset_pll_sys		12
#define reg_resets_reset_pio1			11
#define reg_resets_reset_pio0			10
#define reg_resets_reset_pads_qspi		9
#define reg_resets_reset_pads_bank0		8
#define reg_resets_reset_jtag			7
#define reg_resets_reset_io_qspi		6
#define reg_resets_reset_io_bank0		5
#define reg_resets_reset_i2c1			4
#define reg_resets_reset_i2c0			3
#define reg_resets_reset_dma			2
#define reg_resets_reset_busctrl		1
#define reg_resets_reset_adc			0
			

	reg_clr(reg_resets_reset)
		= (1<<reg_resets_reset_io_bank0)
		| (1<<reg_resets_reset_uart0);
			

Bring GPIO bank 0 and UART0 out of reset. Note we used the atomic clear operation to prevent unintended reset of other functionalities.

#define reg_io_bank0_gpio_ctrl(io)	(0x40014004 + 8 * io)
#define reg_io_bank0_gpio_ctrl_irqover		29
#define reg_io_bank0_gpio_ctrl_irqover_normal	0
#define reg_io_bank0_gpio_ctrl_irqover_invert	1
#define reg_io_bank0_gpio_ctrl_irqover_low	2
#define reg_io_bank0_gpio_ctrl_irqover_high	3
#define reg_io_bank0_gpio_ctrl_inover		16
#define reg_io_bank0_gpio_ctrl_inover_normal	0
#define reg_io_bank0_gpio_ctrl_inover_invert	1
#define reg_io_bank0_gpio_ctrl_inover_low		2
#define reg_io_bank0_gpio_ctrl_inover_high	3
#define reg_io_bank0_gpio_ctrl_oeover		12
#define reg_io_bank0_gpio_ctrl_oeover_normal	0
#define reg_io_bank0_gpio_ctrl_oeover_invert	1
#define reg_io_bank0_gpio_ctrl_oeover_low		2
#define reg_io_bank0_gpio_ctrl_oeover_high	3
#define reg_io_bank0_gpio_ctrl_outover		8
#define reg_io_bank0_gpio_ctrl_outover_normal	0
#define reg_io_bank0_gpio_ctrl_outover_invert	1
#define reg_io_bank0_gpio_ctrl_outover_low	2
#define reg_io_bank0_gpio_ctrl_outover_high	3
#define reg_io_bank0_gpio_ctrl_funcsel		0
#define reg_io_bank0_gpio_ctrl_spi			1
#define reg_io_bank0_gpio_ctrl_uart			2
#define reg_io_bank0_gpio_ctrl_i2c			3
#define reg_io_bank0_gpio_ctrl_pwm			4
#define reg_io_bank0_gpio_ctrl_sio			5
#define reg_io_bank0_gpio_ctrl_pio0			6
#define reg_io_bank0_gpio_ctrl_pio1			7
#define reg_io_bank0_gpio_ctrl_clock		8
#define reg_io_bank0_gpio_ctrl_usb			9
			

	reg(reg_io_bank0_gpio_ctrl(0))
		= (reg_io_bank0_gpio_ctrl_uart<<reg_io_bank0_gpio_ctrl_funcsel);
	reg(reg_io_bank0_gpio_ctrl(1))
		= (reg_io_bank0_gpio_ctrl_uart<<reg_io_bank0_gpio_ctrl_funcsel);
			

Set the function of GPIO 0 and 1 to UART.

#define reg_clk_peri_ctrl			0x40008048
#define reg_clk_peri_en				11
#define reg_clk_peri_kill			10
#define reg_clk_peri_auxsrc			5
#define reg_clk_peri_auxsrc_sys		0
#define reg_clk_peri_auxsrc_syspll		1
#define reg_clk_peri_auxsrc_usbpll		2
#define reg_clk_peri_auxsrc_roscph		3
#define reg_clk_peri_auxsrc_xosc		4
#define reg_clk_peri_auxsrc_gpin0		5
#define reg_clk_peri_auxsrc_gpin1		6
			

	reg(reg_clk_peri_ctrl)
		= (1<<reg_clk_peri_en)
		| (reg_clk_peri_auxsrc_sys<<reg_clk_peri_auxsrc);
			

The peripheral clock is used to drive UART and it is disabled by default. We need to enable it before we can use the UART. We will use the system clock (which uses system PLL as input) to drive the peripheral clock, clocked at 132MHz.

#define reg_uart_uartibdr(n)		(0x40034024 + 0x4000 * n)
#define reg_uart_uartfbdr(n)		(0x40034028 + 0x4000 * n)
			

There are two sets of UART in RP2040. Base address of UART0 is 0x40034000, base address of of UART1 is 0x40038000.

	reg(reg_uart_uartibdr(0)) = 859;
	reg(reg_uart_uartfbdr(0)) = 24;
			

First, set the BAUD rate. Because the system is clocked at 132MHz and our PC expects the UART signal at 9600 BAUD, the UART clock divisor should be:

132MHz / 9600BAUD / 16 = 859.375
			

where the integer part is 859.

The UART clock divisor allows 6-bit fractional part, which means:

0.375 * (2^6) = 0.375 * 64 = 24
			

where the fractional part should be 24.

#define reg_uart_uartlcr_h(n)		(0x4003402c + 0x4000 * n)
#define reg_uart_uartlcr_h_sps		7
#define reg_uart_uartlcr_h_wlen		5
#define reg_uart_uartlcr_h_fen		4
#define reg_uart_uartlcr_h_stp2		3
#define reg_uart_uartlcr_h_eps		2
#define reg_uart_uartlcr_h_pen		1
#define reg_uart_uartlcr_h_brk		0
			

	reg(reg_uart_uartlcr_h(0))
		= ((8-5)<<reg_uart_uartlcr_h_wlen)
		| (1<<reg_uart_uartlcr_h_fen)
		| (1<<reg_uart_uartlcr_h_stp2);
			

Then, the line control, which means the UART frame format. We will use:

• 8-bit data length.
• Using the Tx/Rx FIFO. (32 words depth in both direction)
• 2 stop bits. Note this only affects the transmitter part. It provides a more reliable signal because it gives longer stop bit length to compensate for clock error.

#define reg_uart_uartcr(n)		(0x40034030 + 0x4000 * n)
#define reg_uart_uartcr_ctsen			15
#define reg_uart_uartcr_rtsen			14
#define reg_uart_uartcr_out2			13
#define reg_uart_uartcr_out1			12
#define reg_uart_uartcr_rts			11
#define reg_uart_uartcr_dtr			10
#define reg_uart_uartcr_rxe			9
#define reg_uart_uartcr_txe			8
#define reg_uart_uartcr_lbe			7
#define reg_uart_uartcr_sirlp			2
#define reg_uart_uartcr_siren			1
#define reg_uart_uartcr_uarten		0
			

	reg(reg_uart_uartcr(0))
		= (1<<reg_uart_uartcr_rxe)
		| (1<<reg_uart_uartcr_txe)
		| (1<<reg_uart_uartcr_uarten);
			

At the end, enable UART, including both Tx (transmitter) and Rx (receiver).

#define reg_uart_uartdr(n)		(0x40034000 + 0x4000 * n)
#define reg_uart_uartdr_oe		11 // Overrun
#define reg_uart_uartdr_be		10 // Break error
#define reg_uart_uartdr_pe		9 // Parity error
#define reg_uart_uartdr_fe		8 // Framing error
#define reg_uart_uartdr_data		0 // Tx/Rx data (FIFO)

#define reg_uart_uartfr(n)		(0x40034018 + 0x4000 * n)
#define reg_uart_uartfr_ri		8 // Ring indicator
#define reg_uart_uartfr_txfe		7 // Tx fifo empty
#define reg_uart_uartfr_rxff		6 // Rx fifo full
#define reg_uart_uartfr_txff		5 // Tx fifo full
#define reg_uart_uartfr_rxfe		4 // Rx fifo empty
#define reg_uart_uartfr_busy		3
#define reg_uart_uartfr_dcd		2 // Data carrier detect
#define reg_uart_uartfr_dsr		1 // Data set ready
#define reg_uart_uartfr_cts		0 // Clear to send
			

	for(;;) {
		while ( reg(reg_uart_uartfr(0)) & (<<reg_uart_uartfr_rxfe) );
		char received = reg(reg_uart_uartdr(0));
			

First, polling the UART flag register for any incoming data. Is the Rx FIFO empty?

If false, read from the Rx FIFO.

#define reg_sio_fifo_st			0xd0000050
#define reg_sio_fifo_st_roe		3		// Read on empty
#define reg_sio_fifo_st_wof		2		// Write on full
#define reg_sio_fifo_st_rdy		1		// Ready to write (not full)
#define reg_sio_fifo_st_vld		0		// Valid to read (not empty)
#define reg_sio_fifo_wr			0xd0000054
			

		while (!( reg(reg_sio_fifo_st) & (1<<reg_sio_fifo_st_rdy) ));
		reg(reg_sio_fifo_wr) = received;
	}
}
			

Next, polling the inter-processor mailbox status register. Is the mailbox ready for new data (not full)?

If true, write the received data into the inter-processor mailbox.

void c1_reset() __attribute__((section(".c1_text"))) __attribute__((naked));

void c1_reset() {
	(boot3_clearInterprocessorMailboxRx + 1)();

	for(;;) {
			

Define the entry point for core 1, function c1_reset. Similar to c0_reset, make it naked, place it in section .c1_text.

At the beginning of this function, call boot3_clearInterprocessorMailboxRx to clear the inter-processor mailbox.

Create a dead loop to perform the following tasks:

#define reg_sio_fifo_rd			0xd0000058
			

		while (!( reg(reg_sio_fifo_st) & (1<<reg_sio_fifo_st_vld) ));
		char received = reg(reg_sio_fifo_rd);
			

Polling the inter-processor mailbox status register. Is the mailbox valid for reading (not empty)?

If true, read the data from the inter-processor mailbox.

		__attribute__((section(".c1_data"))) const static char input[] = "Received character is: ";
			

We will define a string that is:

• __attribute__((section(".c1_data"))) - Place this string in section .c1_data, that is in the same SRAM bank as the program running on core 1 (.c1_text), to prevent any structural hazard (occured if we place it in SRAM banks used by core 0) and cache miss (occured if we place it in flash).
• const - We are not gonna modify this string. This is a hint to the compiler, in other words, the compiler will alert us if we tend to modify it. The compiler will generate the same binary code with or without this keyword.
• static - Do not place this variable in the local frame (in stack).

		for(const char* ptr = input; *ptr; ptr++) {
			while ( reg(reg_uart_uartfr(0)) & (11<<reg_uart_uartfr_txff) );
			reg(reg_uart_uartdr(0)) = *ptr;
		}
			

To print this string, we will use a for-loop:

• Create a pointer to point to this string. In C, this pointer will point to the first character in this string.
• The for-loop breaks when the pointer points to zero. In C, a string ends with a null-terminator, which is represented by a zero.
• In each iteration, the pointer is indexed by 1 character (1 byte).

In the for-loop, before sending each character, polling the UART flag register to check the FIFO. Wait if Tx FIFO full.

Once free (Tx FIFO no longer full), send the character by writing it to the UART data register.

		while (!( reg(reg_uart_uartfr(0)) & (1<<reg_uart_uartfr_txfe) ));
		reg(reg_uart_uartdr(0)) = received;
		reg(reg_uart_uartdr(0)) = '\r';
		reg(reg_uart_uartdr(0)) = '\n';
			

Then, check the UART. Wait until the Tx FIFO is empty. This gives us up to 32 words of space to write.

Once the Tx FIFO is empty, burst write the received character, followed by \r and \n to start a new line on the PC terminal. 3 words in total.

		__attribute__((section(".c1_data"))) const static char output[] = "The next ASCII character is: ";
		for(const char* ptr = input; *ptr; ptr++) {
			while ( reg(reg_uart_uartfr(0)) & (11<<reg_uart_uartfr_txff) );
			reg(reg_uart_uartdr(0)) = *ptr;
		}

		while (!( reg(reg_uart_uartfr(0)) & (1<<reg_uart_uartfr_txfe) ));
		reg(reg_uart_uartdr(0)) = received;
		reg(reg_uart_uartdr(0)) = '\r';
		reg(reg_uart_uartdr(0)) = '\n';
	}
}
			

Send the second message followed by the modified (+1 to its ASCII code) data.

Connect the Pico board to a USB-UART-TTL adapter, use GPIO0 for Tx and GPIO1 for Rx.

Next, connect the adapter to a PC, and open a serial terminal. In this example, I use Putty in Serial mode. Set it to 9600 BAUD.

Type a random character on the keyboard, which sends that character to the RP2040 MCU via UART. For example, type the key '1', whose ASCII code is 0x31.

The RP2040 replies the message with the character we sent ('1') and its next character('2'), as shown in the screenshot.