.cpu cortex-m0plus
.thumb
.align 2
.thumb_func

.section .vector
.global vector
vector:
	.word	0x20041000
	.word	reset + 1

.section .text
.global reset
reset:
	ldr	r7, =0x4000f000		@ RESETS_RESET  + 0x3000
	mov	r0, #(1<<5)		@ IO_BANK0
	str	r0, [r7, #0x00]
	ldr	r7, =0x400140cc		@ IO_BANK0_GPIO25_CTRL
	mov	r0, #5			@ SIO
	str	r0, [r7, #0x00]
	ldr	r7, =0xd0000000		@ SIO_GPIO_BASE
	ldr	r0, =(1<<25)		@ GPIO25
	str	r0, [r7, #0x20]		@ SIO_GPIO_BASE_OE

1:	str	r0, [r7, #0x1C]		@ SIO_GPIO_BASE_XOR
	b	1b
		

This program contains a dead loop which XOR the output.

According to the instruction set document:

1. str r0, [r7, #0x1C] - Writing to the GPIO 25 (SIO) will consume 1 CPU clock cycle.
2. b 1b - Branching with PC modified will consume 2 CPU cycles.

In total, the GPIO 25 flips every 3 CPU cycles, and the wave period will be 6 CPU cycles (3 cycles high, 3 cycles low).

MEMORY {
	SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 264k
	SRAM_4(rwx) : ORIGIN = 0x20040000, LENGTH = 4k
	SRAM_5(rwx) : ORIGIN = 0x20041000, LENGTH = 4k
	SRAM_0(rwx) : ORIGIN = 0x21000000, LENGTH = 64k
	SRAM_1(rwx) : ORIGIN = 0x21010000, LENGTH = 64k
	SRAM_2(rwx) : ORIGIN = 0x21020000, LENGTH = 64k
	SRAM_3(rwx) : ORIGIN = 0x21030000, LENGTH = 64k
}

ENTRY(reset)

SECTIONS {
	.text : {
		*(reset)
	} > SRAM
}
		

Only place the reset routine to SRAM. The vector is not required.

The entry point is reset routine.

MEMORY {
	FLASH(rwx) : ORIGIN = 0x10000000, LENGTH = 2048k
}

SECTIONS {
	.text : {
		*(.boot2)
		*(.vector)
		*(reset)
	} > FLASH
}
		

Place the 2nd stage bootloader .boot at the beginning of flash, as required by the on-chip bootloader. Next, place the vector table vector right after the 2nd stage bootloader, as required by the 2nd stage bootloader. At the end, place the reset routine.

Entry point is not required for flash programming.

arm-none-eabi-as --warn --fatal-warnings -g main.s -o main.o
arm-none-eabi-objdump --disassembler-options=force-thumb -Dxs main.o > main.list

# SRAM
arm-none-eabi-ld -nostdlib -nostartfiles -T sram.ld main.o -o sram.elf
arm-none-eabi-objdump --disassembler-options=force-thumb -dxs sram.elf > sram.list
pico-elf2uf2 sram.elf sram.uf2

# Flash
arm-none-eabi-ld -nostdlib -nostartfiles -T flash.ld main.o boot2.o -o flash.elf
arm-none-eabi-objdump --disassembler-options=force-thumb -dxs flash.elf > flash.list
pico-elf2uf2 flash.elf flash.uf2
		

Compile this project. This generates two uf2 files:

• sram.uf2 - Download and execute from SRAM.
• flash.uf2 - Burn the flash and execute the program from flash, allow the program to be preserved after power cycle.

Now, we can use an oscilloscope to measure the output signal. We will measure the signal at this position, at the high end of the LED resistor. See the above figure for the test point.

As the scope shows, the signal frequency is around 966kHz. Since the wave period is 6 CPU cycles, the CPU is running at around 5.8MHz.

This is far less than the advertised 133MHz.

PR2040 provides a set of clocks, in other words, clock sources. They are shown on the left side of the figure. Note some clock sources are driven by other clock sources.

There are clock generators that select one of the clock sources, then use a divider to decrease the frequency (to save power or to satisfy the consumer’s max frequency). They are shown in the middle of the figure.

The output clock signals are then fed to the consumers, including system (CPU cores), peripherals, clock outputs.

Some clock outputs can be fed to another clock's input. The detail can be found in the clock generator's control registers. Following is what I had analysis:

CLK_GPIO_0 / CLK_GPIO_1

0. CLKSRC_PLL_SYS
1. CLKSRC_GPIN0
2. CLKSRC_GPIN1
3. CLKSRC_PLL_USB
4. ROSC_CLKSRC
5. XOSC_CLKSRC
6. CLK_SYS
7. CLK_USB
8. CLK_ADC
9. CLK_RTC
10. CLK_REF

CLK_GPIO_2 / CLK_GPIO_3

0. CLKSRC_PLL_SYS
1. CLKSRC_GPIN0
2. CLKSRC_GPIN1
3. CLKSRC_PLL_USB
4. ROSC_CLKSRC_PH (phase shift)
5. XOSC_CLKSRC
6. CLK_SYS
7. CLK_USB
8. CLK_ADC
9. CLK_RTC
10. CLK_REF

CLK_REF

0. ROSC_CLKSRC_PH
1. CLKSRC_CLK_REF_AUX
   0. CLKSRC_PLL_USB
   1. CLKSRC_GPIN0
   2. CLKSRC_GPIN1
2. XOSC_CLKSRC

CLK_SYS

0. CLK_REF
1. CLKSRC_CLK_SYS_AUX
   0. CLKSRC_PLL_SYS
   1. CLKSRC_PLL_USB
   2. ROSC_CLKSRC
   3. XOSC_CLKSRC
   4. CLKSRC_GPIN0
   5. CLKSRC_GPIN1

CLK_PERI

0. CLK_SYS
1. CLKSRC_PLL_SYS
2. CLKSRC_PLL_USB
3. ROSC_CLKSRC_PH
4. XOSC_CLKSRC
5. CLKSRC_GPIN0
6. CLKSRC_GPIN1

CLK_USB / CLK_ADC / CLK_RTC

0. CLKSRC_PLL_USB
1. CLKSRC_PLL_SYS
2. ROSC_CLKSRC_PH
3. XOSC_CLKSRC
4. CLKSRC_GPIN0
5. CLKSRC_GPIN1

.cpu cortex-m0plus
.thumb
.align 2
.thumb_func

.section .vector
.global vector
vector:
	.word	0x20041000
	.word	reset + 1

.section .text
.global reset
reset:

@ Switch to XOSC
	ldr	r7, =0x40008000
	mov	r0, #((3<<5) | (0<<0))
	str	r0, [r7, #0x3C]
	nop
	nop
	nop
	nop
	mov	r0, #((3<<5) | (1<<0))
	str	r0, [r7, #0x3C]

@ GPIO
	ldr	r7, =0x4000f000		@ RESETS_RESET  + 0x3000
	mov	r0, #(1<<5)		@ IO_BANK0
	str	r0, [r7, #0x00]
	ldr	r7, =0x400140cc		@ IO_BANK0_GPIO25_CTRL
	mov	r0, #5			@ SIO
	str	r0, [r7, #0x00]
	ldr	r7, =0xd0000000		@ SIO_GPIO_BASE
	ldr	r0, =(1<<25)		@ GPIO25
	str	r0, [r7, #0x20]		@ SIO_GPIO_BASE_OE

1:	str	r0, [r7, #0x1C]		@ SIO_GPIO_BASE_XOR
	b	1b
			

First, change the system clock control register to switch the aux mux and glitchless mux at the same time:

• Change the glitchless mux to use reference clock source. This change can be executed on-the-flay. If the glitchless mux is currently running on the reference clock, this switching has no effect. If the glitchless mux is currently running on the aux mux, this switching gated the will-glitch input.
• Change the aux mux to the desired clock source. In this example, the crystal oscillator.

Wait for 4 cycles (of ROSC). Since ROSC is running at 5.8MHz but the XOSC is running at 12MHz, 4 cycles of ROSC is for sure longer than 2 cycles of ROSC plus 2 cycles of XOSC. Furthermore, loading r0 and writing to the control register also provides extra time.

Now, the aux mux should be stable. We can change the glitchless mux to use the aux mux as its source.

We will use the default clock divider (1).

The glitchless multiplexer does not switch instantaneously (to avoid glitches), it takes a few cycles to actually switch the clock source, the CLOCKS_CLK_SYS_SELECTED register can be used to get the current clock to confirm the clock source is switched. We are not concern about this issue in this example.

.cpu cortex-m0plus
.thumb
.align 2
.thumb_func

.section .vector
.global vector
vector:
	.word	0x20041000
	.word	reset + 1

.section .text
.global reset
reset:

@ Start XOSC
	ldr	r7, =0x40024000
	ldr	r0, =0x00FABAA0
	str	r0, [r7, #0x00]
1:	ldr	r0, [r7, #0x04]
	lsr	r0, #32
	bcc	1b

@ Switch to XOSC
	ldr	r7, =0x40008000
	mov	r0, #((3<<5) | (0<<0))
	str	r0, [r7, #0x3C]
	nop
	nop
	mov	r0, #((3<<5) | (1<<0))
	str	r0, [r7, #0x3C]

@ GPIO
	ldr	r7, =0x4000f000		@ RESETS_RESET  + 0x3000
	mov	r0, #(1<<5)		@ IO_BANK0
	str	r0, [r7, #0x00]
	ldr	r7, =0x400140cc		@ IO_BANK0_GPIO25_CTRL
	mov	r0, #5			@ SIO
	str	r0, [r7, #0x00]
	ldr	r7, =0xd0000000		@ SIO_GPIO_BASE
	ldr	r0, =(1<<25)		@ GPIO25
	str	r0, [r7, #0x20]		@ SIO_GPIO_BASE_OE

1:	str	r0, [r7, #0x1C]		@ SIO_GPIO_BASE_XOR
	b	1b
			

To start XOSC, set the XOSC_CTRL register with ENABLE password and FREQ_RANGE, where the ENABLE must be 0xFAB and FREQ_RANGE must be 0xAA0.

Then, poll the STABLE bit in XOSC_STATUS until the XOSC clock is stable.

Now, XOSC can be used.

.cpu cortex-m0plus
.thumb
.align 2
.thumb_func

.section .vector
.global vector
vector:
	.word	0x20041000
	.word	reset + 1

.section .text
.global reset
reset:

@ Start XOSC
	ldr	r7, =0x40024000
	ldr	r0, =0x00FABAA0
	str	r0, [r7, #0x00]
1:	ldr	r0, [r7, #0x04]
	lsr	r0, #32
	bcc	1b
			

The system PLL and the USB PLL need to use the XOSC as their reference clock. Thereore, we will need to enable XOSC first. Detail of this code can be found in the previous example.

@ Start PLL
	ldr	r7, =0x4000f000
	ldr	r0, =(1<<12)
	str	r0, [r7, #0x00]
			

After power-up, the system PLL is in reset. We will need to write 1 to bring the system PLL out of reset. To preserve the reset status of other components, add 0x3000 to the address for atomically write to clear.

	ldr	r7, =0x40028000
	ldr	r6, =0x40028000 + 0x3000
	mov	r0, #(1<<0)
	str	r0, [r7, #0x00]
	mov	r0, #66
	str	r0, [r7, #0x08]
			

RP2040 comes with two of PLLs, one for system that runs up to 133MHz; another one for USB that runs up to 48MHz. The base address is 0x40028000 for system PLL control registers; and 0x4002C000 for USB PLL control registers.

We will use r7 for base address of the system PLL control registers, use r6 for atomically write to clear system PLL control registers.

First, set the reference clock divider to 1. Since the on-board crystal is 12MHz, this will bring 12MHz / 1 = 12MHz reference signal into the PLL. This setting is helpful if the chip is driven by high frequency clock.

Then, set the feedback divider to 66. This will bring the frequency at VCO to 12MHz * 66 = 792MHz.

	mov	r0, #((1<<5) | (1<<0))
	str	r0, [r6, #0x04]
1:	ldr	r0, [r7, #0x00]
	lsr	r0, r0, #32
	bcc	1b
			

By default, all components in the PLL is powered down. Power-up the VCO and the the PLL to start the PLL, but keep the post divider down.

It takes a while for the frequency to stable and the phase to locked. We can poll the LOCK bit in the PLL_SYS_CS register to confirm when the PLL is ready.

	ldr	r0, =((6<<16) | (1<<12))
	str	r0, [r7, #0x0C]
	mov	r0, #(1<<3)
	str	r0, [r6, #0x04]
			

Set the 2-stage post divider. We use 6 for the first stage and 1 for the second stage, this brings the frequency down to 792MHz / 6 / 1 = 132MHz.

Power up the post divider.

@ Switch to PLL
	ldr	r7, =0x40008000
	mov	r0, #((0<<5) | (0<<0))
	str	r0, [r7, #0x3C]
	nop
	nop
	mov	r0, #((0<<5) | (1<<0))
	str	r0, [r7, #0x3C]
			

Switch the aux and glitchless mux to use the system PLL. Detail of this code can be found in the previous example.